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Circuit design language : ウィキペディア英語版 | Circuit design language
Circuit design language is a kind of netlist, a description of an electronic circuit. It is usually automatically generated from a circuit schematic. It is used for electronic circuit simulation and layout versus schematic (LVS) checks. It is similar to SPICE netlists, but with some extensions. Several vendors such as Cadence Design Systems, Calibre, and Synopsys support CDL netlists, although their solutions may be proprietary and not readable by competing systems.
抄文引用元・出典: フリー百科事典『 ウィキペディア(Wikipedia)』 ■ウィキペディアで「Circuit design language」の詳細全文を読む
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